1. Technical Field
The present invention relates to a test signal generating apparatus in a semiconductor integrated circuit and method for generating the test signal, and in particular, to a test signal generating apparatus in a semiconductor integrated circuit and method for generating the test signal having an increased area margin.
2. Related Art
Generally, in order to produce a semiconductor integrated circuit, a test should be performed for measuring a difference between a simulation result upon design and an operation of a real product. At present, various kinds of tests are performed so as to reduce an error rate of the semiconductor integrated circuit. The tests are performed on the basis of external commands and addresses. Accordingly, the semiconductor integrated circuit needs a test signal generating apparatus that generates a plurality of test signals from the commands and the addresses. The test signals generated by the test signal generating apparatus are used to change the operation in a prescribed area. At this time, some of the test signals should be continuously generated after the test is completed. Accordingly, in order to continuously generate the test signals, the general test signal generating apparatus includes test fuse circuit units corresponding to the number of test signals to be generated.
The fuse circuit unit provided in the general semiconductor integrated circuit is controlled by, for example, a laser or the like. However, the use of the fuse circuit unit that is artificially controlled by the laser makes it difficult to reduce the area of the test signal generating apparatus.
Further, in order to implement the fuse circuit unit, an upper portion of the fuse circuit unit should be empty. Therefore, it is difficult to integrate elements in a laminate shape. This also causes the reduction of the area margin of the semiconductor integrated circuit. In addition, although a few fuse circuit units among many fuse circuit units are actually used by artificial control, according to the related art, one fuse circuit unit is inefficiently prepared for one test signal.